It is thus a general object of the present invention to provide improved digital computers. It then finishes the power up diagnostic testing and starts the CPU.
It is a particular object of the present invention to provide digital computers that may be interconnected to form a highly efficient distributed computing system. 101 (prior art) is a block diagram of a typical prior art general purpose computer employed in a distributed computer network. 102 is a block diagram of the computer of the present invention employed in a distributed computer network. During normal run time, IOC 202 services devices connected to it.
Detailed Description of MBus 2054.1 OVERVIEW4.1.2 Configuration4.2 OPERATION4.2.1 Definitions4.2.2 Signals22.214.171.124 Signal Groups126.96.36.199 Data188.8.131.52 Addresses184.108.40.206 Control Signals220.127.116.11 Interrupt Support4.2.3 Addressing4.2.4 Control Functions18.104.22.168 Basic Read22.214.171.124 Double Read126.96.36.199 Simple Write188.8.131.52 Double Write184.108.40.206 Read-Modify-Write220.127.116.11 Double Read-Modify-Write18.104.22.168 Refresh/Sniff22.214.171.124 ERCC Disable4.2.5 Timing4.2.6 Dynamic RAM Cycle Initialization4.2.7 Interrupt Service4.3 ELECTRICAL CHARACTERISTICS4.3.1 Signal States4.3.2 Signal Types4.3.3 Signal Loading4.3.4 Termination and Pull-ups4.3.5 Timing126.96.36.199 Bus Clock188.8.131.52 Bank Select Setup and Hold184.108.40.206 Address Setup and Hold220.127.116.11 Memory Access18.104.22.168 Write Data Setup and Hold22.214.171.124 MEMWAIT Signal Requirements126.96.36.199 ERCCDIS188.8.131.52 Non-Maskable Interrupts5. 226 through 234 illustrate the timing of various bus control signals in relation to the Bus Clock signal. 235 shows the timing of various control signals relative to the power-up condition. It is two way interleaved to enhance consecutive access performance.
Detailed Description of VCU 2065.1 OVERVIEW5.2 FUNCTIONAL DESCRIPTION5.2.1 Hardware Overview184.108.40.206 Pixel Mode Overview220.127.116.11 Plane Mode Overview5.2.2 Programming Overview18.104.22.168 General22.214.171.124 NORMAL space/OTHER space126.96.36.199 Restrictions188.8.131.52 Access types184.108.40.206 Keyboard and mouse5.3 GRAPHICS DATA PROCESSOR 3145.3.1 Functional Description220.127.116.11 Hardware Overview18.104.22.168 Control Overview22.214.171.124 Detailed Controls5.3.2 Detailed Functional Description126.96.36.199 EXTernal Accesses188.8.131.52 EXTernal PLANE Access184.108.40.206 INTernal Accesses220.127.116.11 Character Accesses18.104.22.168 Using the LALU5.3.3 Timing Diagrams5.4 VCU 206 DETAILED OPERATION5.4.1 Video RAMs5.4.2 Video Output Stage5.4.3 M-Bus Interface5.4.4 Basic Timing22.214.171.124 Video Timing5.4.5 Video Palette5.4.6 Refresh5.4.7 Keyboard5.4.8 Mouse5.4.9 COM DATA/COM STATUS Registers5.4.10 DC/DC Converter5..5.1 Converting from 8 to 24 bits/pixel5.6 PROGRAMMING DESCRIPTION5.6.1 Board Selection/LAR5.6.2 OTHER Space Accesses126.96.36.199 LALU Register188.8.131.52 PLANE ENABLE Register184.108.40.206 FOREGROUND Register220.127.116.11 BACKGROUND Register18.104.22.168 COM DATA Register22.214.171.124 COM STATUS Register126.96.36.199 Keyboard/LED Register188.8.131.52 PIXEL ENABLE Register5.6.3 NORMAL Space Accesses184.108.40.206 Host Accesses220.127.116.11 Internal Accesses18.104.22.168 Character Drawing22.214.171.124 X and Y, SOURCE and DEST Registers5.6.4 READ/WRITE Pixel5.6.5 READ/WRITE Block5.6.6 Interrupts6. 216 through 223 are timing charts pertaining to bus arbitration and bus data transmission. Additional off-board memory may be connected to MBus 205; this may additional main memory 102, or VRAMs 113 for storing screen bit maps (see section 5). 104) is designed to support the base system I/O devices as well as SCP (system console processor) functions.
Detailed Description of VCU 2065.1 Overview5.2 Functional Description5.3 Graphics Data PRocessor 3145.4 Detailed Operation5..6 Programming Description6. LMB 203 The Local Memory Bus is the communication path from the local computer (CPU portion) and from the local I/O portion.
This MBus has expansion capability so that up to 16 Mbytes can be addressed by this MCU (the two gate arrays) without adding more control. The LMB initiates all local memory accesses while the I-Bus initiates all accesses of this particular node from other global nodes. The LMB and the I-Bus are the two busses that can initiate memory operations.1.2 Description of the Prior Art Digital computers in general are well known in the prior art. The I/O function provides the board with device support for the basic integrated I/O devices.Digital computers have been employed in "distributed computing networks" in which a plurality of computers are interconnected and are programmed to cooperate on an overall data processing task involving a related body of data and a related body of tasks to be performed thereon, with some computers doing some of the processing and then passing results or status information to other of the computers which perform other of the processing. This includes: an SCSI (small computer standard interface) Bus Host-Adapter Interface 468 an SA400 Floppy Diskette Controller 467 an Ethernet IEEE802.3 LAN Controller 480 Four RS232C Asynch Channels 459 (1 w/modem support) a parallel Printer Port 460 a battery-backed-up Time-of-Boot Clock/Calendar 457 The Local Memory Bus Interface is the primary communications channel between CPU 101, IOC 202, and MCU 201.